Nonvolatile memory apparatuses are commonly mounted in portable devices such as cellular phones or digital cameras and the use of them has being spreading at a rapid pace. In recent years, in many cases, audio data and image data have been used. Accordingly, there has been a strong demand for nonvolatile memory apparatuses which have larger capacities and operate at high speeds so as to store data at a speed substantially equal to the speed of a logic operation as in SRAM. Furthermore, in fields of nonvolatile memory apparatuses for use with portable devices, a demand for lower electric power consumption has been increasing.
At present, a major nonvolatile memory apparatus is a flash memory. The flash memory is configured to control electric charges accumulated on a floating gate to store data. It has been pointed out that since the flash memory has a structure for accumulating electric charges on the floating gate at a high electric field, there is a limitation to reduction of the size, and it is difficult to miniaturize the flash memory, which is required to provide a larger capacity. In addition, in the flash memory, specified blocks must be erased all at once for rewriting. Because of such a property, the flash memory requires a very long time for rewriting and has a limitation to an increase in the speed which has been demanded as described above.
As a nonvolatile memory apparatus in next generation capable of solving the above mentioned problem, there is a nonvolatile memory apparatus which uses a resistance variable element for storing data according to a change in electric resistance. As nonvolatile memories using resistance variable elements proposed currently, there are a MRAM (magnetic RAM), PRAM (phase-change RAM), ReRAM (resistive RAM), etc. It has been reported that especially the ReRAM causes a simple phenomenon in which the resistance value changes according to electric pulses and provides high-speed performance in which writing occurs with several tens nseck or less. That is, there is a likelihood that an ultimate memory apparatus which has nonvolatility and operates at a high speed as in the SRAM as described above is attainable using the ReRAM.
Patent document 1 discloses an example of a control method of the ReRAM element (hereinafter also referred to as a resistance variable element) using an oxide of perovskite structure. Now, the control method of the ReRAM element will be described with reference to the drawings.
FIGS. 9 to 11 are views showing the control method of the memory cell disclosed in Patent document 1. A memory cell 9 includes a resistance variable element 1 and a selection transistor 2. One terminal of the resistance variable element 1 is electrically connected to one main terminal (drain or source) of the selection transistor 2. The other main terminal (source or drain) of the selection transistor 2 is electrically connected to a source line terminal 3 via a source line 6. The other terminal of the resistance variable element 1 is electrically connected to a bit line terminal 5 via a bit line 8. A gate of the selection transistor 2 is electrically connected to a word line terminal 4 via a word line 7. In any of the cases where data is written (“1” is written), data is erased (“0” is written) and data is read, a high-level ON-voltage is applied to the word line terminal 4 of the selected memory cell, causing the selection transistor 2 to be placed in an electrically conductive state.
FIG. 9 is a view showing a state of application of voltage pulses during a write operation in the memory cell of Patent document 1. The source line 6 is set to 0V (electrically grounded), and a positive write pulse having a predetermined write voltage amplitude is applied to the bit line 8 to write desired data to the resistance variable element 1. In the case where multi-valued data is written to the resistance variable element 1, a voltage amplitude of a write pulse is set to a level according to the value of data to be written. For example, in the case where four-valued data is written to one resistance variable element 1, one voltage amplitude is selected from among specified four voltage amplitudes determined to respectively correspond to the values of the write data and a write operation is performed. As a write pulse width, a proper width according to the element is selected. That is, to change the element 1 to a predetermined resistance state, one voltage amplitude level and one pulse width corresponding to the resistance state exist.
FIG. 10 is a view showing a state of application of voltage pulses during an erase operation in the memory cell of Patent document 1. The bit line is set to 0V (electrically grounded) and a positive erase pulse having a predetermined erase voltage amplitude is applied to the source line. With the application of the erase pulse, the electric resistance of the resistance variable element 1 is caused to have a minimum value. Patent document 1 discloses that, upon application of the erase pulse to a specified source line with plural bit lines set to 0V, data are erased all at once from plural memory cells connected to the plural bit lines and to the source line.
FIG. 11 is a view showing a state of application of a voltage pulse during a read operation in the memory cell of Patent document 1. When reading data stored in the resistance variable element 1, the source line 6 is set to 0V (electrically grounded), and a predetermined read voltage is applied to the selected bit line 8 via a read circuit. Upon application of the read voltage, a comparison/determination circuit compares a level of the bit line 8 to a reference level for reading, and stored data is read.
Non-patent document 1 discloses a ReRAM element configured to transition between a high-resistance state and a low-resistance state by application of voltage pulses having the same polarity and different voltages and pulse widths. TMO (transition metal oxide) is used as a resistance variable material for the ReRAM element of Non-patent document 1. The ReRAM element is capable of being changed to a high-resistance state or to a low-resistance state in response to the electric pulses of the same polarity. FIG. 12 is a view showing a voltage-current characteristic of the ReRAM element of Non-patent document 1. As shown in FIG. 12, in “SET” in which the element is switched from the high-resistance state to the low-resistance state, a more current than before flows when the element has been switched from the high-resistance state to the low-resistance state unless a set current compliance is used. In this case, even though the ReRAM element has been switched from the high-resistance state to the low-resistance state, re-switching of the resistance state may occur, in which the element switches from the low-resistance state to the high-resistance state unexpectedly (incorrect operation), or the element may be broken due to an excess current. Non-patent document 1 discloses that it is necessary to use a set current compliance of a first predetermined current value (upper limit value of a current in the set current compliance in FIG. 12).    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2004-185756    Non-patent document 1: Baek, I. G. et al., 2004, “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, 0-7803-8684-1/04/$20.00IEEE